The present invention relates to integrated circuits, and more particularly, to integrated circuit impedance devices. There are typically a limited number of device types that are used in making most integrated circuits. The most common devices are the N-channel and P-channel transistors. Most logical functions can be implemented using a combination of only these two devices. However, some applications may require additional device types.
In one application, for example, resistors may be incorporated into a data storage circuit to increase the Single Event Upset (SEU) hardness of the data storage circuit. The resistors are typically connected in a cross-coupled configuration, as shown in FIG. 1. The cross-coupled resistors increase the SEU hardness of the data storage circuit by increasing the feedback delay around the data storage circuit. The increased delay provides the data storage circuit more time to remove any charge that is deposited during a radiation event. A further discussion of the use of resistors to increase the SEU hardness of a data storage circuit can be found in co-pending U.S. patent application Ser. No. 09/219,807, filed Dec. 23, 1998, entitled "SEU Hardening Circuit", which is incorporated herein by reference.
For many integrated circuit processes, such as MOSFET type process, the resistors are formed using a single polysilicon layer. The polysilicon layer is often the same polysilicon layer that is used to form the gates of the N-channel and P-channel transistors. The polysilicon layer of the N-channel and P-channel transistors is usually covered with a silicide layer to further enhance the conductivity thereof To make the polysilicon layer more resistive, therefore, a silicide blanking step must typically be performed. The silicide blanking step blanks the silicide layer from those locations that correspond to the polysilicon resistors. Additional processing may also be requires, such as selective implant processing, to achieve the desired resistance values. Because of this additional processing, the cost of producing such integrated circuits may be increased.
In addition, when such polysilicon resistors are used in conjunction with a typical gate array, the achievable gate density of the gate array may be reduced. In a typical gate array, such as a Sea-Of-Gates (SOG) gate array, all of the underlayers are typically prefabricated. The polysilicon and silicide layers are usually part of the pre-fabricated underlayers. To personalize the gate array, one or more metal layers are used to interconnect the pre-fabricated devices.
To make the polysilicon resistors widely available, the resistors are typically distributed among the standard transistors. For most circuits, however, only a small fraction of the gates require a resistor. For example, in a radiation-hard integrated circuit, only selected data storage circuits (e.g. latches, flip-flops, etc.) may need cross-coupled resistors to achieve a desired SEU hardness. The remaining circuits, including much of the combinational logic, typically does not need polysilicon resistors. Therefore, and because the resistors are typically distributed across the gate array, most of the resistors go un-used. These un-used resistors consume valuable silicon real-estate which could otherwise be used for transistors to increase the gate density of the gate array.
Therefore, it would be desirable to provide a device that can serve a dual function as either an impedance (e.g. resistor) or a standard transistor, depending on the metal interconnect layers provided. It would also be desirable if the device did not require any additional processing steps relative to those required for a conventional transistor.